최신ARM Accredited engineer - EN0-001무료샘플문제

A. Floating point calculations have lower performance than hardware floating point

B. Not all floating point arithmetic operations are supported

C. The resulting code will be larger

D. The results of floating point calculations will be less accurate

E. The stack cannot be used to pass floating point function arguments

A. Active to Inactive

B. Active to Pending

C. Pending to Active

D. Inactive to Active

A. Active to Inactive

B. Pending to Active

C. Inactive to Active

D. Inactive to Pending

A. A uni-core Cortex-A5 processor with a digital signal processor (DSP)

B. A Cortex-R4 processor with a Cortex-M3 system controller

C. A Cortex-A8 processor with a graphics processing unit (GPU)

D. A dual-core Cortex-A9 processor

A. To tell the compiler that an object can be on an unaligned address

B. To tell the compiler to use only Thumb code

C. To tell the compiler to produce code of minimum size

D. To tell the compiler not to perform padding inside structures

E. To tell the compiler to use the v6 SIMD pack/unpack instructions

A. 208

B. 204

C. 200

D. 201

A. 8

B. 4

C. 1

D. 7

A. Registers

B. Hard disk

C. Stack

D. Heap

A. DSBST

B. DMBSY

C. DMBST

D. DSBSY

A. A write to Strongly-ordered memory is permitted to complete before it reaches the peripheral or memory component accessed by the write

B. Address locations marked as Strongly-ordered memory are never held in a cache

C. The number and size of accesses to Strongly-ordered memory must be the same as that specified by the program

D. The architecture does not permit speculative data accesses to Strongly-ordered memory

A. Interrupt from a shared peripheral to a processor

B. Interrupt from a processor to a shared peripheral

C. Interrupt from a private peripheral to a processor

D. Interrupt from a private peripheral to a shared peripheral

E. Interrupt from a processor to a private peripheral

F. Interrupt from a shared peripheral to a private peripheral

A. Level 3

B. Level 2

C. Level 1

D. Level 4

A. Contents of the Level 1 data cache

B. All User mode general-purpose registers

C. The CP15 Multiprocessor Affinity Register

D. Current Program Status Register (CPSR)

E. The Floating Point Status and Control Register (FPSCR)

F. Contents of the Level 2 data cache

A. Hardware specific source code needed for operating system support

B. PC interface hardware for configuring a boot monitor

C. A working port of Linux for a specific hardware platform

D. Debugging hardware and software supplied with a development board

A. a->d0; b->d1; c->d2

B. a->s0; b->d1; c-> s2

C. a->s0; b->d0; c->s1

D. a->s0; b->d1; c->s1